Selectively decoupled I/O latch

Details Selectively decoupled I/O latch Selectively decoupled I/O latch

1996-11-26

1998-10-27

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365154, G11C 700

Patent

active

058286080

ABSTRACT:
A selectively decoupled latch circuit used for latching a signal. The circuit contains an input line for accepting an input signal to the circuit. A latch is connected to the input line for latching the input signal. A transfer gate is also connected to the input line and latch for transferring the input signal to the latch according to a clock signal. A transistor is connected in a series with a feedback loop associated with the latch. The transistor selectively decouples the feedback path according to the clock signal. By selectively decoupling the feedback path, it is easier for a new input signal to become latched because contention between a prior latched signal versus the new input signal is minimized. An output line is connected to the latch for outputting a latched signal.

REFERENCES:
patent: 4654826 (1987-03-01), Yamanouchi et al.
patent: 5541881 (1996-07-01), Miller
patent: 5615146 (1997-03-01), Gotou

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