Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2001-03-30
2002-09-24
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S194000, C365S233500
Reexamination Certificate
active
06456544
ABSTRACT:
BACKGROUND
This invention is generally related to digital solid state memories and more particularly to source synchronous input/output (I/O) in a memory subsystem where the strobe signal is either asserted, deasserted, or not driven by a memory device.
In a memory subsystem that operates in a source synchronous manner, the device which transmits a data signal on a conductive data line also transmits a strobe signal on a separate conductive line. A pulse in the strobe signal has a predefined phase relationship to each associated pulse in a number of data signals. The pulse in the strobe signal is used to capture bit values in the data signals at the receiving device. This is done by running the data and strobe signals through receiver circuitry which detects the logic levels that are being asserted, and translates them into voltage levels that are suitable for processing by controller circuitry in an integrated circuit (IC) die. The outputs of the receiver circuitry are then fed to a number of latches each of which captures a bit value in a respective data signal in response to a pulse in the strobe signal.
According to certain high speed signaling requirements, the strobe receiver circuit at its front end should have a two input comparator, where each input is terminated at the same termination voltage, which may be half-way between a logic ‘0’ voltage and a logic ‘1’ voltage. The strobe line coming from the memory device is shorted to one of the inputs. The comparator's output at any time indicates the logic state being detected on the strobe line, as either ‘0’ or ‘1’ depending upon whether the strobe signal is being asserted or deasserted by the memory device. The output of the comparator directly feeds the clock input of a latch. A data input of the latch receives a level-translated version of the data signal. The latch thus captures a bit value in the data signal upon every low/high to high/low transition of the comparator output. In other words, the latched bit values are always dictated by the strobe signal. The latter is also referred to here as ‘continuously forwarding’ the strobe signal.
In some high speed memory specifications such as double data rate (DDR) synchronous dynamic random access memory (SDRAM), as defined by the Joint Electronic Device Engineering Council (JEDEC) Solid State Technology Association in their publication,
DDR SDRAM Specification
(
JESD
79), June 2000, a memory device must neither assert or deassert the strobe signal when it is not providing any data in response to a read command. In other words, when no read data is being transferred, the memory device should not drive the strobe line to a ‘0’ or ‘1’ voltage. This, however, causes a problem at the receiving device when the strobe line floats to the termination voltage, thereby causing the comparator output to become unstable due to the now essentially equal input voltages. This instability in turn will cause the unacceptable result that unintended bit values are captured by the latch from the data line.
REFERENCES:
patent: 5488581 (1996-01-01), Nagao et al.
patent: 5812492 (1998-09-01), Yamauchi et al.
patent: 6112284 (2000-08-01), Hayek et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Lam David
LandOfFree
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