Self adjusting pre-charge delay in memory circuits and methods f

Details Self adjusting pre-charge delay in memory circuits and methods f Self adjusting pre-charge delay in memory circuits and methods f

1997-09-12

1999-03-09

Nelms, David

Static information storage and retrieval

Read/write circuit

Differential sensing

365203, 3652335, G11C 702

Patent

active

058810080

ABSTRACT:
An embedded memory device structure, and a method for making the embedded memory device structure having self adjusting pre-charge delay characteristics. The method includes selecting a desired memory array having a dummy column of cells. Coupling a pre-charge detect circuit to the dummy column of cells. The pre-charge detect circuit is configured to measure an activation and pre-charge response time of cells contained within the dummy column of cells. Transferring the activation and pre-charge response time to an address transition detect unit. The method further includes generating a custom clock timing signal in response to the activation and pre-charge response time of cells contained within the dummy column of cells.

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