Selective bit line recovery in a memory array

Details Selective bit line recovery in a memory array Selective bit line recovery in a memory array

1997-09-26

1999-03-16

Nelms, David

Static information storage and retrieval

Read/write circuit

For complementary information

365203, G11C 700

Patent

active

058838414

ABSTRACT:
A selective recovery circuit and method for a memory array allows bit line recovery after a write operation on a selective basis so that only those column circuits actually written are recovered to at least non-write voltage levels. For each column circuit within the memory array, a recovery signal generation circuit is provided to determine whether the column circuit was actually written and to generate a recovery signal if the column circuit was written. Each column circuit includes a recovery circuit coupled to the bit line pair which, in response to the recovery signal, restores the voltage level of the bit lines of the column circuit back to an at least non-write voltage level. Other columns which are not actually written by the write operation include those not selected by the column decode circuitry, as well as those selected by the column decode circuitry but which correspond to a non-enabled byte of the data word. The recovery circuit for these non-written column circuits is not activated after the write operation, which results in a substantial savings in power. In one embodiment, the voltage levels of the bit lines are sensed to determine whether the column circuit was written, and the recovery signal is initiated upon deactivation of a signal controlling the write operation. The recovery signal may be coupled to an equilibrate transistor as well, which equilibrates the bit lines after a write operation. The invention is particularly well-suited to use within a static RAM-based cache memory array for a processor having byte enable capability, such as an X86-compatible processor.

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