Built-in redundancy architecture for computer memories
Byte aligned redundancy for memory array
Byte aligned redundancy for memory array
Byte organized static memory
Byte writeable memory with bit-column voltage selection and...
CBR refresh control for the redundancy array
Cell data margin test with dummy cell
Cell-based integrated circuit design repair using gate array rep
Chip information managing method, chip information managing...
Chip information managing method, chip information managing...
Circuit and method for a multiplexed redundancy scheme in a memo
Circuit and method for a multiplexed redundancy scheme in a...
Circuit and method for column redundancy for high bandwidth memo
Circuit and method for controlling a redundant memory cell in an
Circuit and method for detecting defects in semiconductor...
Circuit and method for enabling a function in a multiple memory
Circuit and method for enabling a function in a multiple memory
Circuit and method for repairing column in semiconductor...
Circuit and method for replacing a defective memory cell with a
Circuit and method for testing multi-device systems