Circuit and method for column redundancy for high bandwidth memo

Details Circuit and method for column redundancy for high bandwidth memo Circuit and method for column redundancy for high bandwidth memo

1999-09-17

2000-09-19

Mai, Son

Static information storage and retrieval

Read/write circuit

Bad bit

36518912, 365219, G11C 700

Patent

active

061222089

ABSTRACT:
A memory device includes a base memory with a defective memory cell. A read circuit with a serial output port and parallel input ports is connected to the base memory. The read circuit converts parallel read data received at the parallel input ports to a first serial data stream, which is applied to the serial output port. The first serial data stream includes a faulty bit corresponding to the defective memory cell. A spare memory stores a spare bit corresponding to the defective memory cell. A bit insertion circuit is connected to the spare memory and the serial output port of the read circuit. The bit insertion circuit substitutes the faulty bit value of the first serial data stream with the spare bit.

REFERENCES:
patent: 4691301 (1987-09-01), Anderson
patent: 5005158 (1991-04-01), McClure et al.
patent: 5274593 (1993-12-01), Proebsting
patent: 5497353 (1996-03-01), Sato et al.
patent: 5768196 (1998-06-01), Bloker et al.
patent: 5953745 (1999-09-01), Lattimore et al.

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