Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-08-10
2001-06-26
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700, C365S230080, C365S189070, C365S203000, C365S193000
Reexamination Certificate
active
06252810
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a circuit and a method for detecting defects in a semiconductor memory, particularly to a circuit and a method for replacing a defective cell or a line in a semiconductor memory having spare row lines and column lines (bit lines and word lines) with a spare line (cell).
BACKGROUND OF THE INVENTION
Many semiconductor-memory products such as DRAMs use the so-called defect relieving method for improving the yield of memory products by using spare row lines and column lines (bit lines and word lines) and replacing these space row lines or column lines with row lines or column lines in which a defect occurs. A defect detection circuit is a circuit for comparing an accessed address with an address previously assigned to a spare row line and column line and determining whether to replace the former address with the latter address.
FIG. 1
is an illustration showing a conventional defect detection circuit. Circuit
1
is a circuit for holding an address determined to be a defect when testing a memory product as previously-programmed information (hereafter referred to as program information) by using a fuse or the like. Circuit
2
is a circuit for renewing and holding an address accessed (inputted) in read or write operation as address information. Though the number of pieces of address information to be inputted depends on a configuration of a memory, 10 to 14 pieces of the address information are required. Circuit
3
is a circuit for comparing program information outputted from Circuit
1
with address information outputted from Circuit
2
and determining whether to select a spare line.
FIG. 2
is an illustration showing a configuration of the comparing and detection Circuit
3
in FIG.
1
. In
FIG. 2
, the program information (i
th
) outputted from the Circuit
1
is compared with the address information (i
th
) outputted from the Circuit
2
by an exclusive NOR Circuit
4
. Then, comparison results are accumulated by a combinational Circuit
5
comprising a NAND circuit and a NOR circuit and when all the comparison results are matched, a result of replacement with spare lines is outputted.
The compare and detection Circuit
3
in
FIG. 2
usually optimizes a combinational circuit comprising logical gates and the size of a transistor to be used. However, because of a large number of inputs such as 10 to 14, the combinational Circuit
5
requires logical gates of at least three stages as shown in FIG.
2
. As a result, a problem occurs that it takes a lot of time to output a comparison and selection result.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a circuit and a method for detection of defects in a semiconductor memory operating at a high speed.
Another object of the present invention is to provide a circuit and a method for detection of defects in a semiconductor memory operating at a high speed without greatly increasing a circuit area.
The present invention provides a circuit for detecting defects in a semiconductor memory having spare row lines and column lines, comprising:
a program-information holding circuit for holding program information showing addresses previously assigned to spare row lines or column lines;
an address-information refreshing and holding circuit for refreshing and holding address information in row lines and column lines to be accessed in read or write operation; and
a compare and detection circuit for comparing program information outputted from the program-information holding circuit with address information outputted from the address-information refreshing and holding circuit and determining whether to replace a row line or column line to be accessed with a spare row line or column line; wherein
the address-information refreshing and holding circuit has a function of previously holding the program information outputted from the program-information holding circuit at the end of the last operation as address information.
The present invention provides a method for detection of defects in a semiconductor memory having spare row lines and column lines, comprising the steps of:
holding program information showing addresses previously assigned to spare row lines and column lines;
holding address information in row lines and column lines to be accessed in read or write operation inputted from an external unit; and
comparing the held program information with the held address information and determining whether to replace a row line or column line to be accessed with a spare row line or column line; wherein
the address-information holding step includes the step of previously holding the program information held at the end of the last operation as address information.
REFERENCES:
patent: 4718041 (1988-01-01), Baglee et al.
patent: 62-188100 (1987-08-01), None
International Business Machines - Corporation
Tran Andrew Q.
Walsh Robert A.
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