Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2006-12-19
2008-10-28
Le, Thong Q (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189011, C365S189140, C365S189040
Reexamination Certificate
active
07443745
ABSTRACT:
A method for accessing a memory comprising a first set of bit columns, a second set of bit columns, and a redundant set of bit columns, wherein any one of the redundant set of bit columns can be substituted for one of the first set of bit columns or one of the second set of bit columns and wherein each of the bit columns can receive a read voltage or a write voltage, is provided. The method includes during a write operation to the first set of bit columns, providing the write voltage to one of the redundant set of bit columns, if the one of the redundant set of bit columns has been substituted for one of the first set of bit columns, otherwise providing the read voltage to the redundant set of bit columns.
REFERENCES:
patent: 6480415 (2002-11-01), Makuta et al.
patent: 6556479 (2003-04-01), Makuta et al.
patent: 2005/0024981 (2005-02-01), Bateman et al.
patent: 2006/0034137 (2006-02-01), Zanardi
K. Zhang, et al., “A 3-Ghz 70Mb SRAM in 65nm CMOS Technology with Integrated Column-Based Dynamic Power Supply”, IEEE International Solid-State Circuits Conference 2005, pp. 474, 475, 611.
Freescale Semiconductor Inc.
Le Thong Q
Singh Ranjeev
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