Cell data margin test with dummy cell

Details Cell data margin test with dummy cell Cell data margin test with dummy cell

2005-09-27

2005-09-27

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S233100

Reexamination Certificate

active

06950353

ABSTRACT:
A memory array includes a true bitline and a complementary bitline and a sense amplifier connected thereto; a row of normal cells with capacitors for data storage and bitline storage capacitors. A row of dummy cells with dummy cell capacitors is also provided. A clock provides wordline drive signals to the normal cells. When operating in the test mode, the clock provides at least one dummy wordline drive signal to the dummy cell switch in response to a testing signal for connecting the dummy cell capacitor to the bitline. A plurality of rows of dummy cells can be employed with various permutations of actuation thereof to provide various levels of capacitance connected to the bitlines in the test mode.

REFERENCES:
patent: 4468759 (1984-08-01), Kung et al.
patent: 5544108 (1996-08-01), Thomann
patent: 5592427 (1997-01-01), Kumakura et al.
patent: 6104650 (2000-08-01), Shore
patent: 6614690 (2003-09-01), Roohparvar
patent: 2004/0242009 (2004-12-01), Banks

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