CBR refresh control for the redundancy array

Static information storage and retrieval – Read/write circuit – Bad bit

Reexamination Certificate

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C365S222000

Reexamination Certificate

active

06195300

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor memories and, in particular, to a method and system for refreshing memory cells in a semiconductor memory.
BACKGROUND OF THE INVENTION
Generally, dynamic random access memories (DRAMS) are organized in a structure of two-dimensional cells in rows and columns. Memory cells may be accessed via wordlines, which are driven from row paths. Each cross point realizes an access to cell information of each cell connected to a selected wordline.
To achieve a high yield efficiency in semiconductor memories, redundancy array architecture is employed. Redundancy arrays are described by: Kalter et al., in “A 50-ns 16 MB DRAM with a 10-ns Rate and On-Chip ECC”, IEEE Solid-State Circuits, Vol. 25, No. 5, Oct. 1990; and T. Kirihata, in “Fault-Tolerant Designs for 256 Mb DRAM”, IEEE Solid-State Circuits, Vol. 31, No. 4, Apr. 1996, pp. 558-566. To distinguish non-redundancy memory arrays, cells, and wordlines from redundancy memory arrays, cells, and wordlines, the former group are hereinafter referred to as normal memory arrays, cells, and wordlines.
Redundancy array architecture allows a defective normal wordline WL
i
in any normal array to be replaced with a redundancy wordline RWL
k
in the redundancy array. In this scheme flexibility is high, and the number of reparable normal wordlines is increased.
FIG. 1
is a diagram illustrating a common structure of a DRAM that includes a plurality of normal memory arrays
110
and a redundancy memory array
112
, according to the prior art. A random access mode and a Cas-Before-Ras (CBR) mode of the DRAM arrays are depicted on the left and right sides of
FIG. 1
, respectively.
The random access mode allows data to be read from, or written to, DRAM cells coupling the corresponding normal wordline WL
i
in the activated normal memory array
110
i
(in a normal random access mode). If the normal wordline WL
i
is defective, it is replaced with the redundancy wordline RWL
k
in the redundancy memory array
112
, allowing data to be read from, or written to, the DRAM cells coupling to the redundancy wordline RWL
k
(in a redundancy random access mode).
Due to the volatile nature of data storage in a DRAM cell, the DRAM includes a refresh operation that recharges the data of the DRAM cells. This refresh operation is generally enabled by a Cas-Before-Ras (CBR) command, and is called in a CBR mode. The CBR mode allows data to be refreshed for the DRAM cells coupling the corresponding normal wordline WL
i
in the activated normal memory array
110
i
(in a normal CBR mode). If the normal wordline WL
i
is defective, it is replaced with the redundancy wordline RWL
k
in the redundancy memory array
112
(in a redundancy CBR mode).
As the DRAM density increases, a CBR mode should activate more memory arrays (e.g.,
110
i
and
110
j
) simultaneously than those activated in a random access mode. This is because activating more arrays refreshes more cells simultaneously in the CBR mode, thereby improving the random access mode utilization. Such a refreshing technique is commonly used for 64 Mb and larger DRAMs.
When a CBR mode needs to activate more than one memory array in the DRAM, there is a possibility of having more than one normal wordline WL
i
and WL
j
simultaneously replaced with the corresponding redundancy wordlines RWL
k
and RWL
l
, respectively. In this case, the chip becomes irreparable, because the bit data accessed by the redundancy wordlines RWL
k
and RWL
l
are conflicted on the bit-lines of the redundancy memory array
112
. That is, since the pair of normal wordlines WL
i
and WL
j
are typically addressed together at the same time, they cannot be replaced with redundant wordlines in the redundancy memory array
112
. This is because the row address signal addressing the pair of wordlines at the same time can address only one redundant wordline at a time in the redundancy memory array
112
. While the use of two redundancy arrays would overcome the preceding problem, such use requires additional area to support the two redundancy arrays. Further, as the DRAM density increases, more wordlines may be activated simultaneously in a CBR mode. This increases the probability of the redundancy array contention.
Accordingly, based on the above description of the prior art, it would be desirable and highly advantageous to have a method that solves the problem of redundancy access contention in a CBR mode, without increasing the DRAM chip size.
SUMMARY OF THE INVENTION
The problem stated above, as well as other related problems of the prior art, are solved by the present invention, a method and system for refreshing memory cells in a semiconductor memory. According to the present invention, normal memory cells and redundancy memory cells are independently refreshed, using a row address counter and a redundancy address counter, respectively. Preferably, redundancy memory cells are refreshed during the process of refreshing the normal memory cells, since no additional cycle time would be required. By using the master fuse signal, the redundancy memory cells accessed by only programmed redundancy wordlines are refreshed, avoiding the potential problem caused by selecting defective redundancy wordlines. Thus, the present invention advantageously solves the problem of having more than one redundancy wordline in the redundancy array selected simultaneously, while successfully refreshing the redundancy memory cells.
According to a first aspect of the invention, there is provided a method for refreshing memory cells in semiconductor memories. The method includes the steps of providing a semiconductor memory having normal memory cells and redundancy memory cells in at least one normal memory array and an associated redundancy memory array, respectively. The normal memory cells and the redundancy memory cells are independently refreshed, using addresses generated by a row address counter and a redundancy address counter, respectively.
According to a second aspect of the invention, the method further includes the step of disabling redundancy wordlines coupled to unused redundancy memory cells, using a master fuse signal corresponding to a master fuse of the semiconductor memory.
According to a third aspect of the invention, the method further includes the step of disabling wordlines coupled to defective memory cells.
According to a fourth aspect of the invention, the disabling step is performed in one of Cas-Before-Ras (CBR) refresh mode, a self refresh mode, and an auto refresh mode.
According to a fifth aspect of the invention, the refreshing step includes the step of refreshing only the redundancy memory cells accessed by programmed redundancy wordlines, using a master fuse signal corresponding to a master fuse of the semiconductor memory.
According to a sixth aspect of the invention, the method further includes the step of independently and simultaneously refreshing the normal memory cells and the redundancy memory cells in a refresh mode.
According to a seventh aspect of the invention, the method further includes the step of activating a plurality of redundancy memory cells corresponding to a given wordline, when a normal wordline address ADR corresponding to the given wordline is detected in the random access mode that has been preprogrammed by a plurality of fuses.
According to an eighth aspect of the invention, the activating step is performed in the random access mode.
According to a ninth aspect of the invention, the refreshing step is performed in one of a Cas-Before-Ras (CBR) refresh mode, a self refresh mode, and an auto refresh mode.
According to a tenth aspect of the invention, the normal memory cells and the redundancy memory cells are refreshed simultaneously.
According to an eleventh aspect of the invention, there is provided a system for refreshing memory cells in a semiconductor memory. The semiconductor memory has normal memory cells and redundancy memory cells in at least one normal memory array and an associated redundancy memory array, respectively. The sy

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