Built-in redundancy architecture for computer memories

Details Built-in redundancy architecture for computer memories Built-in redundancy architecture for computer memories

1998-06-22

2000-06-06

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, 36523006, G11C 700

Patent

active

060727357

ABSTRACT:
A computer main memory is divided into multiple physically-separated arrays of memory cells. Each array has associated with it an array of spare memory cells. The array of spare memory cells is located adjacent to its associated main memory cell array. The rows in the spare memory cell array are aligned with the rows in the associated main memory cell array. The main memory blocks are divided into subblocks. Within each subblock, all columns are addressed by a single multiplexer unique to that subblock. A data input bus and a data output bus is provided corresponding to each subblock in the main memory block. Each data input bus and data output bus is electrically coupled to a main memory bus, and each spare memory block. Data can therefore be readily directed either to one of the subblocks in the main memory or to one of the spare memory blocks.

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