Byte aligned redundancy for memory array

Details Byte aligned redundancy for memory array Byte aligned redundancy for memory array

2002-12-05

2004-12-14

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

06831868

ABSTRACT:

BACKGROUND OF THE INVENTION
In semiconductor memories, a redundancy scheme is often employed that allows defective portions of a memory array to be effectively replaced using spare segments in the array. In this manner, manufacturing yields can be increased and overall manufacturing costs reduced. One redundancy scheme that is commonly employed is known as column redundancy. In a memory implementing column redundancy, a spare (or redundant) column is used to compensate for a defective column within an array. In one known column redundancy technique, data bits within a row of a memory array are shifted one bit position to the right (or left) from the location of a defective column to bypass the defective column. The least significant bit of the row is shifted into the redundant column of the memory array. Upon reading the data from the row, the displaced data bits are shifted back to their intended bit positions. This redundant shifting may be performed for a row in the corresponding memory array.
In a memory supporting byte access, an individual byte of data may be written to and/or read from a row of a memory array (the row being larger than a single byte) without accessing the entire row. In such memories, read and/or write controls are often implemented on a byte-by-byte basis. Redundant bit shifts that cross byte boundaries within the array can therefore require additional read and/or write controls to be generated during a byte access operation that would not normally be necessary, for example, a control to read a bit of data from or write a bit of data to an adjacent byte in a row of the array. The need to generate these additional controls adds complexity to the overall memory design and will typically require a significant increase in the amount of control logic and routing necessary to support redundancy within a memory.


REFERENCES:
patent: 6172916 (2001-01-01), Ooishi
patent: 6552937 (2003-04-01), Ladner et al.
patent: 6704226 (2004-03-01), Lee
patent: 6728910 (2004-04-01), Huang

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