Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-10-13
2001-07-31
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189020
Reexamination Certificate
active
06269035
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to memory devices, and more particularly to a circuit and method for replacing defective memory cells in a memory device using redundant memory cells.
BACKGROUND OF THE INVENTION
A typical semiconductor memory device includes a memory-cell array containing a plurality memory cells arranged in rows and columns. The memory cells in the array are typically tested and, if necessary, repaired before the memory devices are shipped to customers. During testing of the memory device, any of the memory cells that are found to be defective are replaced with a redundant memory cell. The entire row or column containing the defective memory cell is typically replaced with a redundant row or column, respectively. For example, to replace a row containing a defective memory cell, a row address decoder is programmed to map a redundant row to the address of the row containing the defective memory cell, and to disable data access to the row containing the defective memory cell. Therefore, when an external circuit reads data from or writes data to this detective row address, the row address decoder does not activate the defective row, but instead activates the redundant row so that data may be transferred to or from a corresponding addressed memory cell within the redundant row.
Substitution of a redundant row or column is conventionally accomplished by opening a specific combination of fuses, or closing a combination of antifuses, in one of several fuse banks on the die in which the memory device is formed. Conventional fuses include polysilicon fuses, which can be opened by laser trimming, and also include avalanche-type fuses and capacitive-type antifuses. If a given row or column in the array contains a defective memory cell, the address of that defective memory cell is programmed into the fuse bank. A compare circuit compares each incoming address to determine whether the incoming address matches any of the addresses programmed in the fuse banks. If the compare circuit determines a match, it outputs a match signal to a row or column decoder. In response, the row or column decoder accesses the appropriate redundant row or column, and ignores the defective row or column in the primary memory array.
Although it would appear that having more redundant memory for the memory device would be advantageous, the rows and columns of redundant memory cells, as well as the compare circuitry necessary for accessing the redundant rows and columns, occupy considerable space on the die of the memory device. Compare circuits typically employ multiple exclusive OR gates which require a greater amount of area than other logic gates, such as NAND and NOR gates. At least one compare circuit is required for each bank of fuses. On the other hand, reducing the number of redundant rows and columns may result in an insufficient number of redundant rows and columns to repair the memory device.
Exacerbating the problem with reducing the number of redundant memory elements is the fact that the primary memory array is divided into several sub-arrays. Conventional memory devices divide the primary array of memory cells into sub-arrays so that only a portion of the memory need be energized during a given access. This results in significant power reduction. However, the problem is that within each sub-array, there are a limited number of redundant rows and columns available to repair the defective memory cells located in the sub-array. The associated redundant rows and columns can be used only to repair defective memory cells located within the particular sub-array, or group of sub-arrays. If there are more defective memory cells in a sub-array than can be repaired by the redundant memory available in that sub-array, the entire memory device must be discarded.
There is a need for increasing the repairability of a memory device by replacing defective memory cells with redundant memory while minimizing any increase in the amount of redundant memory in the memory device.
SUMMARY OF THE INVENTION
A memory device having a memory cell array divided into several memory sub-arrays maps unused redundant memory of one memory sub-array to repair defective memory in another memory sub-array in order to increase memory repairability without increasing the number of redundant rows or columns. Each sub-array has a limited number of redundant memory. When the limited number of redundant memory is depleted for a memory sub-array, the memory device can still be repaired by mapping unused redundant memory of another memory sub-array to the address of the defective memory cell. The sub-arrays sharing unused redundant memory are coupled through a respective isolation circuit to common I/O lines. A control circuit is coupled to the isolation circuit to selectively couple the redundant memory to the appropriate I/O line and facilitate the use of the redundant memory of one memory sub-array to repair defective memory of another memory sub-array. The substitution appears transparent to the remainder of the memory device.
REFERENCES:
patent: 4660179 (1987-04-01), Aoyama
patent: 4727516 (1988-02-01), Yoshida et al.
patent: 5268866 (1993-12-01), Feng et al.
patent: 5293348 (1994-03-01), Abe
patent: 5349556 (1994-09-01), Lee
patent: 5359560 (1994-10-01), Suh et al.
patent: 5491664 (1996-02-01), Phelan
patent: 5848003 (1998-12-01), Nishikawa
patent: 5894441 (1999-04-01), Nakazawa
Cowles Timothy B.
Cullum James S.
Wong Victor
Wright Jeffrey P.
Dorsey & Whitney LLP
Mai Son
Micro)n Technology, Inc.
LandOfFree
Circuit and method for a multiplexed redundancy scheme in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit and method for a multiplexed redundancy scheme in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for a multiplexed redundancy scheme in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2445604