Byte aligned redundancy for memory array

Details Byte aligned redundancy for memory array Byte aligned redundancy for memory array

2006-01-10

2006-01-10

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

06985392

ABSTRACT:
A memory includes byte aligned column redundancy capabilities for use in repairing the memory when a defective column is present. The memory array includes a repair/redundant column for use in repairing the memory when another column of the memory array is defective. The memory also has a redundant write multiplexer to select, when a defective column is present in the memory array, an input data bit to be written to the redundant column. A first input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the first column group and a second input of the redundant write multiplexer may be coupled to receive either the LSB or the MSB of write data associated with the second column group.

REFERENCES:
patent: 6172916 (2001-01-01), Ooishi
patent: 6178127 (2001-01-01), Haraguchi
patent: 6304501 (2001-10-01), Ooishi
patent: 6366509 (2002-04-01), Shirley
patent: 6552937 (2003-04-01), Ladner et al.
patent: 6704226 (2004-03-01), Lee
patent: 6724669 (2004-04-01), Bhatia
patent: 6728910 (2004-04-01), Huang

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