Decoding hierarchical architecture for high integration memories

Decoding of a register file

Decoding structure for a memory device with a control code

Deep pipe synchronous SRAM

Delay apparatus

Delay line and output clock generator using same

Delay lock loop circuit useful in a synchronous system and...

Delay lock loop circuit useful in a synchronous system and...

Delay locked loop (DLL) in semiconductor device

Delay locked loop control circuit

Delay locked loop device

Delay locked loop for use in synchronous dynamic random...

Delay locked loop for use in synchronous dynamic random...

Delay locked loop implementation in a synchronous dynamic random

Delay locked loop implementation in a synchronous dynamic...

Delay locked loop implementation in a synchronous dynamic...

Delay locked loop monitor test mode

Delay locking high speed clock synchronization method and...

Delay mechanism for unbalanced read/write paths in domino...

Delay mechanism for unbalanced read/write paths in domino...