Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-06-12
2007-06-12
Dinh, Son (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189070, C365S194000, C327S158000, C327S159000
Reexamination Certificate
active
09970388
ABSTRACT:
A delay locked loop (DLL) for compensating for a skew in a synchronous dynamic random access memory includes: a delay model means for delaying an external clock signal by the skew to generate a delayed clock signal; a control unit, in response to the external clock signal and the delayed clock signal, for generating control signals, wherein the control signal includes a control clock signal, a delayed control signal, a replication signal and a replication enable signal; a first voltage controlled oscillator, in response to the control clock signal and the delayed control signal, for generating a measurement oscillating signal; a second voltage controlled oscillator, in response to the replication signal and the replication enable signal, for generating a replication oscillating signal; a first unit, in response to the measurement oscillating signal and the replication oscillating signal, for generating a DLL clock signal; and a second unit for comparing a phase difference between the DLL clock signal and the external clock signal to generate a voltage control signal, wherein time periods of the measurement oscillating signal and the replication oscillating signal are changed by the voltage control signal.
REFERENCES:
patent: 5109394 (1992-04-01), Hjerpe et al.
patent: 5463337 (1995-10-01), Leonowich
patent: 5926047 (1999-07-01), Harrison
WP 24.5 A250Mb/s/pin 1Gb Double Data Rate SDRAM with a Bi-Directional Delay and an Inter-Bank Shared Redundancy Scheme, 1999 IEEE International Solid-State Circuits Conference.
WP 24.2 A2.5V333Mb/s/pin 1Gb Double Sata Rate SDRAM, 1999 IEEE International Solid-State Circuits Conference.
Dinh Son
Hynix / Semiconductor Inc.
Townsend and Townsend / and Crew LLP
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