Delay locked loop implementation in a synchronous dynamic random

Details Delay locked loop implementation in a synchronous dynamic random Delay locked loop implementation in a synchronous dynamic random

1994-10-06

1998-08-18

Zarabian, A.

Static information storage and retrieval

Addressing

Sync/clocking

327284, G11C 800

Patent

active

057966737

ABSTRACT:
A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

REFERENCES:
patent: 4754164 (1988-06-01), Flora
patent: 5287319 (1994-02-01), Fukumoto
patent: 5311483 (1994-05-01), Takasugi

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