Delay locked loop monitor test mode

Details Delay locked loop monitor test mode Delay locked loop monitor test mode

2001-08-30

2002-05-07

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S193000, C365S194000, C327S156000

Reexamination Certificate

active

06385129

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to memory devices, and in particular to monitoring a delay locked loop (DLL) of a memory device.
BACKGROUND OF THE INVENTION
Memory devices are widely used in many electronic products and computers to store data. A memory device includes a number of memory cells. Each cell stores one bit of data. The data stored in the memory cells can be read during a read operation.
One type of memory device includes a reference signal to accompany data signals during a read operation. The reference signal, commonly known as a strobe, is used to track the output timing of the data signals read from the memory cells. In some traditional memory devices, the strobe signal is generated by a delay locked loop (DLL). In these devices the DLL turns on the strobe signal only during a read operation, which requires a read command to be issued to the memory device. Therefore, the characteristics of the DLL in the traditional SDRAM devices cannot be monitored until the read command is issued.
For the reasons stated above, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need to monitor a DLL in a memory device without requiring a read command to be issued to the memory device.
SUMMARY OF THE INVENTION
The present invention includes a memory device having a DLL. The DLL can be monitored at any time by turning on a strobe signal provided by the DLL. The strobe signal can be turned on without a read command being issued.
In one aspect, the memory device includes a clock input buffer to receive an external clock signal to produce an internal clock signal. A DLL receives the internal clock signal to produce a delayed signal. A strobe circuit receives the delayed signal to provide a strobe signal, and a strobe enable circuit connects to the strobe circuit. The strobe enable circuit includes an input to receive a control signal during a test mode to turn on the strobe signal without a read command being issued to the memory device.
In another aspect, a method of operating a memory device includes producing an internal clock signal from an external clock signal. A delayed signal is generated from the internal clock signal. The method also includes producing a strobe signal from the delayed signal. During a read operation, a first control signal is activated to turn on the strobe signal after a read command is issued. The strobe signal can also be turned on by activating a second control signal during a test mode, in which the strobe signal is turned on without a read command being issued.


REFERENCES:
patent: 5754838 (1998-05-01), Shibata et al.
patent: 6259288 (2001-07-01), Nishimura
patent: 6288585 (2001-09-01), Bando et al.
patent: 6295245 (2001-09-01), Tomita et al.

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