Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-10-31
2001-12-25
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189070, C365S194000, C327S158000, C327S159000, C327S161000
Reexamination Certificate
active
06333896
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit; and, more particularly, to a delay locked loop for use in synchronous dynamic random access memory, which is capable of obtaining a fast locking time and a reduced jitter.
DESCRIPTION OF THE PRIOR ART
For achieving a high speed operation in a semiconductor memory device, a synchronous dynamic access memory (SDRAM) has been developed. The SDRAM operates in synchronization with an external clock signal. The SDRAM includes a single data rate (SDR) SDRAM, a double data rate (DDR) SDRAM, and the like.
Generally, when data are outputted in synchronization with the external clock signal, a skew between the external clock signal and the output data is occurred. In the SDRAM, a delay locked loop (DLL) can be used to compensate for the skew between an external clock signal and an output data, or an external clock signal and an internal clock signal.
A digital DLL is implemented with a plurality of unit delay elements that are coupled in series. For increasing a resolution, a unit delay time should be minimized. As the unit delay time becomes smaller, however, more unit delay elements are needed. Consequently, power consumption as well as a chip size is increased much more.
SUMMARY OF THE INVENTION
It is, therefore an object of the present invention to provide a delay locked loop which is capable of obtaining a fast locking time and a reduced jitter by combining a digital locking operation with an analog locking operation.
In accordance with an aspect of the present invention, there is provided a delay locked loop (DLL) for compensating for a skew in a synchronous dynamic random access memory, comprising: a delay model means for delaying an external clock signal by the skew to generate a delayed clock signal; a control means, in response to the external clock signal and the delayed clock signal, for generating control signals, wherein the control signal includes a control clock signal, a delayed control signal, a replication signal and a replication enable signal; a first voltage controlled oscillation means, in response to the control clock signal and the delayed control signal, for generating a measurement oscillating signal; a second voltage controlled oscillation means, in response to the replication signal and the replication enable signal, for generating a replication oscillating signal; a first means, in response to the measurement oscillating signal and the replication oscillating signal for generating a DLL clock signal; and a second means for comparing a phase difference between the DLL clock signal and the external clock signal to generate a voltage control signal, wherein time periods of the measurement oscillating signal and the replication oscillating signal are changed by the voltage control signal.
REFERENCES:
patent: 5926047 (1999-07-01), Harrison
patent: 6011732 (2000-01-01), Harrison et al.
patent: 6018259 (2000-01-01), Lee
patent: 6201424 (2001-03-01), Harrison
patent: 6208183 (2001-03-01), Li et al.
WP 24.5 A250Mb/s/pin 1 Gb Double Data Rate SDRAM with a BI-Directional Delay and an Inter-Bank Shared Redundancy Scheme, 1999 IEEE International Solid-State Circuits Conference.
WP 24.2 A2.5V333Mb/s/pin 1 Gb Double Data Rate SDRAM, 1999 IEEE International Solid-State Circuits Conference.
Dinh Son T.
Hynix / Semiconductor Inc.
Townsend and Townsend / and Crew LLP
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