Decoding hierarchical architecture for high integration memories

Details Decoding hierarchical architecture for high integration memories Decoding hierarchical architecture for high integration memories

1997-01-30

1998-12-29

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Plural blocks or banks

36523002, 36523004, 36523006, 395444, G11C 800

Patent

active

058547703

ABSTRACT:
A nonvolatile static memory includes a matrix of elementary cells addressable through bit-lines (columns) and word-lines (rows) mutually orthogonal among each other, the matrix being divided in two orders of subblocks, respectively left and right, aligned in a direction of extension of the word-lines and symmetrical by pairs. At least one row predecoding circuit and a plurality of row decoding circuits are provided for the subblocks. Column predecoding circuits and a plurality of column multiplexers are provided for the subblocks and controlled by the column predecoding circuits. A first main predecoding circuit of the address bus generates a first bus, a second bus and a third bus. In addition, a pair of main row decoding circuits combines signals of the first, second and third buses and generates a resulting number of main row decoding lines, each stimulating respective row decoding circuits of the right and left subblocks. Two pairs of local row predecoding circuits are provided for each of the right and left subblocks, a first pair for word-lines of even order and a second pair for word-lines of odd order of the right and left subblocks, respectively, and are stimulated by the address bus to generate a fourth bus and a fifth bus, respectively.

REFERENCES:
patent: 5642323 (1997-06-01), Kotani et al.
patent: 5657265 (1997-08-01), Yoo et al.

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