SAM data selection on dual-ported DRAM devices

Scalable N-port memory structures

Scan path circuitry including an output register having a flow t

Scheme for eliminating page boundary limitation on initial acces

Scheme for increasing enable access speed in a memory device

SDRAM address mapping optimized for two-dimensional access

SDRAM and method for data accesses of SDRAM

SDRAM having data latch circuit for outputting input data in...

SDRAM having posted CAS function of JEDEC standard

SDRAM with a maskable input

Search apparatus

Sectional column activated memory

Segmented bus architecture for improving speed in integrated cir

Segmented memory architecture and systems and methods using...

Segmented MRAM memory array

Segmented, multiple-decoder memory array and method for programm

Selectable clock input

Selectable clock input

Selectable memory word line deactivation

Selectable memory word line deactivation