Delay mechanism for unbalanced read/write paths in domino...

Details Delay mechanism for unbalanced read/write paths in domino... Delay mechanism for unbalanced read/write paths in domino...

2008-07-15

2008-07-15

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S154000, C365S189050

Reexamination Certificate

active

07400550

ABSTRACT:
A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_wl and write_wl signals are generated by the wordline decoder based on whether a read or a write operation is to be performed in the next cycle. The wordline decoder includes a buffer having an input for receiving the write_wl signal and an output for outputting a delayed version of the write_wl signal. The wordline signal is activated by the wordline decoder based on the read_wl signal and the delayed write_wl signal. This overcomes the “early read” problem in which write performance is degraded due to a fast read path.

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