Delay locked loop device

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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Details

C365S194000, C327S158000

Reexamination Certificate

active

07099232

ABSTRACT:
An apparatus for detecting locking information of a DLL clock in a semiconductor memory device includes a delayed locked loop for generating a first comparison signal and a first delay end signal; a phase state storing block for receiving the first comparison signal and the first delay end signal to thereby generate a locking selection signal; and a locking information detector for generating a locking state signal presenting the locking information in response to the first comparison signal, the first delay end signal and the locking selection signal.

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patent: 6201424 (2001-03-01), Harrison
patent: 6222894 (2001-04-01), Lee
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patent: 6333959 (2001-12-01), Lai et al.
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patent: 6499111 (2002-12-01), Mullarky
patent: 6518807 (2003-02-01), Cho
patent: 6556488 (2003-04-01), Han
patent: 6570815 (2003-05-01), Kashiwazaki
patent: 01-305634 (1989-12-01), None
patent: 11-126479 (1999-05-01), None
patent: 2001-023383 (2001-01-01), None

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