Delay locked loop implementation in a synchronous dynamic...

Details Delay locked loop implementation in a synchronous dynamic... Delay locked loop implementation in a synchronous dynamic...

2006-01-31

2006-01-31

Tran, Michael (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C327S284000

Reexamination Certificate

active

06992950

ABSTRACT:
A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

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