Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2005-05-10
2005-05-10
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C327S277000, C375S257000, C326S020000
Reexamination Certificate
active
06891774
ABSTRACT:
A delay line for an adjustable, high speed clock generator is based on two-stage multiplexing, in which for all pairs of adjacent taps, a change from a current tap to an adjacent tap in the pair is executed by switching only one of the first stage and second stage multiplexers. Control signals are generated for the first and second stage multiplexers by logic based on bidirectional shift registers. The delay line is suitable for generation of an output clock having an adjustable phase, allowing for smooth, glitch-free adjustment over a large range of phases.
REFERENCES:
patent: 5243227 (1993-09-01), Gutierrez, Jr. et al.
patent: 5298866 (1994-03-01), Kaplinsky
patent: 5424980 (1995-06-01), Vinal
patent: 5432747 (1995-07-01), Fuller et al.
patent: 5561692 (1996-10-01), Maitland et al.
patent: 5596539 (1997-01-01), Passow et al.
patent: 5703815 (1997-12-01), Kuhara et al.
patent: 5805872 (1998-09-01), Bannon
patent: 5831924 (1998-11-01), Nitta et al.
patent: 5999482 (1999-12-01), Kornachuk et al.
patent: 6025744 (2000-02-01), Bertolet et al.
patent: 6081462 (2000-06-01), Lee
patent: 6084805 (2000-07-01), Pawlowski
patent: 6154417 (2000-11-01), Kim
patent: 6157231 (2000-12-01), Wasson
patent: 6160754 (2000-12-01), Suh
patent: 6205086 (2001-03-01), Hanzawa et al.
patent: 6212117 (2001-04-01), Shin et al.
patent: 6229161 (2001-05-01), Nemati et al.
patent: 6243784 (2001-06-01), Anderson et al.
patent: 6278637 (2001-08-01), Kawaguchi
patent: 6318707 (2001-11-01), Hara et al.
patent: 6337830 (2002-01-01), Faue
patent: 6337832 (2002-01-01), Ooishi et al.
patent: 6369624 (2002-04-01), Wang et al.
patent: 6392957 (2002-05-01), Shubat et al.
patent: 6430075 (2002-08-01), Morgan et al.
patent: 6459652 (2002-10-01), Lee et al.
patent: 6462359 (2002-10-01), Nemati et al.
patent: 6490206 (2002-12-01), Kwon et al.
patent: 20010043482 (2001-11-01), Takeyama et al.
patent: 20020190265 (2002-12-01), Hsu et al.
patent: 20030001651 (2003-01-01), La Rosa
patent: 20030002355 (2003-01-01), Janzen et al.
patent: 20030128598 (2003-07-01), Lim et al.
patent: WO 02082453 (2002-10-01), None
patent: WO 02082504 (2002-10-01), None
Nemati, Farid et al., “A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device,” T-Ram White Paper, VLSI (1998) 2 pages, http://www.t-ram.com/technology/about/vlsi98.pdf.
Nemati, Farid et al., “A Novel Thyristor-Based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-scale Memories,” T-Ram White Paper, IEDM (1999), 4 pages http://www.t-ram.com/technology/about/iedm99.pdf.
Abdollahi-Alibeik Shahram
Huang Chaofeng
Elms Richard
Haynes Beffel & Wolfeld LLP
Nguyen N.
T-Ram, Inc.
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