Delay line and output clock generator using same

Details Delay line and output clock generator using same Delay line and output clock generator using same

2005-05-10

2005-05-10

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C327S277000, C375S257000, C326S020000

Reexamination Certificate

active

06891774

ABSTRACT:
A delay line for an adjustable, high speed clock generator is based on two-stage multiplexing, in which for all pairs of adjacent taps, a change from a current tap to an adjacent tap in the pair is executed by switching only one of the first stage and second stage multiplexers. Control signals are generated for the first and second stage multiplexers by logic based on bidirectional shift registers. The delay line is suitable for generation of an output clock having an adjustable phase, allowing for smooth, glitch-free adjustment over a large range of phases.

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