Delay lock loop circuit useful in a synchronous system and...

Details Delay lock loop circuit useful in a synchronous system and... Delay lock loop circuit useful in a synchronous system and...

2002-08-29

2004-01-20

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C327S156000, C327S157000, C327S158000

Reexamination Certificate

active

06680874

ABSTRACT:

BACKGROUND
The present invention relates to computer systems having synchronous data transfer interfaces and also to synchronous memory devices that interface with a synchronous data bus. More particularly, the present invention relates to a delay lock loop of a synchronous memory that comprises an initialization circuit for initializing the delay lock loop to a stable and reliable operating condition.
Known prior art computer systems include processors that exchange data with a variety of memory and input/output peripheral devices. Exemplary memory devices include read only memory (ROM), dynamic random access memory (DRAM), and/or static random access memory (SRAM). Exemplary input/output peripheral devices may include a keyboard, mouse, printer or video display unit. These exemplary memory and peripheral devices typically exchange data with a processor by way of a data bus.
Synchronous dynamic random access memories (SDRAMs) employ pipelined data transfers to a processor or bus for effecting data transfer rates that are comparable to the processor's operating frequency. However, because the processor's operating frequency might be different from that of the SDRAM, a memory controller may be required between the SDRAM and the processor for accommodating their different operating speeds.
Synch-link DRAM (SLDRAM), another known type of memory, exchanges data in packet formats, wherein packets of data are sent or received, as determined in accordance with a received command packet, directly to or from a processor and in synchronous relationship thereto. Additionally, if communicating directly with a processor, the SLDRAM may not require an intermediate memory controller.
In accordance with one such exemplary prior art SLDRAM system architecture, and method of operation, a master clock propagates from a processor to a plurality of SLDRAMs to assist system synchronization, with an aim of facilitating synchronous transfer of data between the processor and memory devices. As a part of this synchronization scheme, the master clock might be used to provide the basis for the generation or correlation of signals within the SLDRAM.
With reference to
FIGS. 1 and 2
, an exemplary, prior art SLDRAM, hereinafter memory
10
, is coupled to a bus
12
. Memory
10
includes an output latch
14
and buffer
15
. Data is sent from these devices to bus
12
via output terminal
21
. The memory also sends a clock signal, which corresponds to that which was used to capture data within latch
14
, to a terminal
23
via delay element
13
and buffer
16
. The output clock signal is provided to facilitate the transfer of data across bus
12
to other devices, e.g., such as a processor. Ideally, for these signals that are output from the memory's output terminals, and referencing the waveforms of
FIG. 2
, transitions
32
of the data signal
28
coincide with the rising or falling edges
34
of the clock signal
30
.
A synchronous relationship is also desired for a data signal and an accompanying clock signal when writing into the memory. Referencing
FIGS. 3 and 4
, a memory
10
is coupled to bus
12
, which bus comprises N data lines
24
and M clock lines
26
. Terminal
39
of memory
10
receives a data signal (e.g., waveform
43
of FIG.
4
), which data signal is internally coupled to the data input of latch
33
. Terminal
45
receives a clock signal (waveform
42
of
FIG. 4
) that is forwarded to the clock input
36
of data latch
33
by way of delay unit
35
. Preferably, delay unit
35
provides an amount of delay T
d1
that appropriately positions a rising edge of the delayed clock signal
44
to a time placement t
1
, relative the data signal, which time placement is coincident with the center of the data eye of the data signal
43
received at the data input of latch
33
. However, the amount of delay that is required for optimal placement of the clock edge may change dependent upon design parameters of the data latch
33
, such as its input capacitance, and any RC time constants associated with the delay circuit
35
. In addition, the memory's supply voltage and its operating temperature can affect the desired optimal placement of the clock edge. Further pushing these synchronization needs, increases in computer speeds are making the processing systems less tolerable of timing changes that might be effected by voltage or temperature variations. Accordingly, delay lock loops and associated vernier circuits have been used to attempt calibration, adjustment and/or compensation of these timing changes that occur over a circuit's lifetime.
A known exemplary delay lock loop is shown as a part of memory
10
in FIG.
5
. Memory
10
receives command data from data lines
24
of bus
12
, at terminals
39
A via command data lines
38
A. Write data is received at terminal
39
B via lines
38
B. A system clock of clock lines
26
, is received at terminal
41
by way of line
40
, while the clock signal associated with the synchronous write data transfer is received at terminal
45
via line
46
. The command data that is received at terminal
39
A is forwarded to the data input of command latch
66
after passing through buffers
65
. A command clock is presented to the latch input of command latch
66
by way of a previously programmed vernier select circuit
64
. Vernier select circuit
64
comprises vernier
60
and multiplexer
62
. Vernier
60
receives the command clock and provides a plurality of variously delayed representations of the command clock at the CCLK
1
-CCLKN outputs. Having been previously programmed in a known fashion, multiplexer
62
selects a particularly delayed representation of the clock signal for selecting an edge placement of the selected delayed clock signal that is to be substantially coincident with centers of eye patterns of the data signal received at the data input of latch
66
. This delayed clock signal, which selection is routed by multiplexer
62
, is forwarded as the latching clock signal to the command latch
66
for use in capturing the command data therein.
A signal from one of the outputs of vernier A, typically the output of greatest delay, e.g., CCLKN, is fed back as the variably delayed signal of the delay lock loop to variable input
70
of phase detector
72
. The phase detector
72
compares the phase of the signal at variable input
70
to that of the reference signal received at reference input
74
. The reference signal corresponds to the received system clock, but delayed by an amount associated with the propagation delay of buffer
73
. Phase detector
72
generates an error signal at its output
75
in accordance with the detected phase difference between the variably delayed signal and the reference signal. Integrator
76
receives the error signal from phase detector
72
and generates a tune voltage (Vtune) by integrating the error signal. The tune voltage from the integrator is coupled to the control input of vernier A and is used for adjusting the amount of delay that is provided by vernier A. Upon acquiring a locked condition, the delay lock loop aims to keep the phase of the variably delayed signal at variable input
70
coincident with that of the reference clock. Thus, the delay lock loop strives to preserve the integrity of data reception by, ideally, keeping a latching edge of the selected, vernier-delayed clock signal centered within the data eye of the data signal that is received at the data input of latch
66
.
When channeling command data to memory
10
, the external system, e.g., a processor, supplies a continuous system clock on line
40
, which runs continuously over time. On the other hand, when transferring write data that is to be written into the memory device, the clock that accompanies the write data on line
46
may be discontinuous, i.e., present only for a duration for accompanying the data transfer. Because the accompanying data clock is not continuous, a separate “slaved” vernier circuit
48
is configured for selecting optimally delayed representations of the data clock for latchi

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