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Buffer memory for an input line of a digital interface

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Buffer storage including a swapping circuit

Static information storage and retrieval – Addressing
Patent

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Buffer using two-port memory

Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate

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Buffering circuit in a semiconductor memory device

Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Reexamination Certificate

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Built-in precision shutdown apparatus for effectuating...

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Burst architecture for a flash memory

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Burst counter circuit and method of operation thereof

Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Patent

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Burst EDO memory address counter

Static information storage and retrieval – Addressing – Byte or page addressing
Patent

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Burst EDO memory device

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Burst EDO memory device

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Burst EDO memory device

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Burst EDO memory device

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Burst EDO memory device address counter

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Burst EDO memory device with maximized write cycle timing

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Burst mode flash memory

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Burst operations in memories

Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate

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Burst order control circuit and method thereof

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Burst page access unit usable in a synchronous DRAM and other se

Static information storage and retrieval – Addressing – Byte or page addressing
Patent

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Burst page access unit usable in a synchronous DRAM and other se

Static information storage and retrieval – Addressing – Byte or page addressing
Patent

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Burst read addressing in a non-volatile memory device

Static information storage and retrieval – Addressing – Counting
Reexamination Certificate

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