Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-08-19
2003-07-22
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S210130, C365S230060, C365S194000, C365S195000, C365S191000, C365S190000, C365S154000
Reexamination Certificate
active
06597629
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates generally to semiconductor memories. More particularly, and not by way of any limitation, the present invention is directed to a self-referenced memory access timing scheme using a built-in precision shutdown apparatus integrated within a memory row decoder.
2. Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a “design gap” between today's electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers' productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the “deep submicron” problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that analog blocks, non-volatile memory, random access memories (RAMs), and other “non-logic” cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take hundreds of staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design re-use is through what are known as Intellectual Property (“IP”) components—pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system. Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory is a key technology driver for SOC design. It is also well known that performance parameters such as access time, overall memory cycle time, power consumption, et cetera, play a pivotal role in designing a memory circuit, whether provided in an embedded SOC application or as a stand-alone device. These parameters can be critically dependent on the topology of a memory array. For high performance memories, accordingly, it is desirable that parameters such as access time, power consumption during access operations, and the like, are optimized regardless of the memory array sizes.
To achieve efficiency, access operations in most memories today are provided to be self-timed. That is, memory accesses typically require only a rising edge of an external clock signal, which is used to manufacture an internal memory clock that provides a time base for access operations. A shutdown signal is subsequently generated for effectuating access shutdown. Thus, in essence, a Self-Timed Clock (STCLK or STC) is imposed on the memory accesses.
Many techniques are available for effectuating the self-timed access clock in current memories. Regardless of the implementational variations, the basic concept remains the same: selecting a particular array wordline (WL) based on address signals specified for an access operation, monitoring array bitline(s) (BLs) to determine if they have discharged to a particular level, and turning off the WL at an appropriate time.
It should be appreciated that the conventional STC schemes are highly sensitive to the array sizes because the electrical characteristics—therefore, timing delays—are topology-dependent. As a consequence, while a specific self-timed access loop arrangement may be satisfactory with respect to a memory device of particular size and aspect, it may be entirely inadequate for other memory sizes. This deficiency is especially exacerbated in compilable memories which, by definition, are capable of generating numerous memory instances having different array sizes, aspect ratios, and I/O configurations, thereby necessitating different STC settings to optimize memory access operations.
In addition, more significantly, the current STC schemes in any implementation give rise to a significant area increase in the memory circuit's layout due to the necessity of the separate self-timed access loop components such as the reference decoder/driver block, RWL block, et cetera. Further, memory accesses timed with a conventional STC arrangement are beset with undesirable dead times, which not only impact access speed, but also give rise to a high amount of power consumption in the memory core due to the fact that the pulse width during which a selected wordline must be driven HIGH for effectuating the access operation is not optimized.
SUMMARY OF THE INVENTION
Accordingly, the present invention advantageously provides a self-referenced, built-in access shutdown mechanism preferably integrated within a row decoder of a memory circuit that obviates the need for separate circuitry and associated areas required for generating a self-timed clock. Instead of using a separate reference decoder/driver block and reference wordline path in the access timing loop, a wordline selected for accessing a core cell itself is utilized for referencing a shutdown sequence. A pair of complementary reference bitlines (BLS and BLE) are operable with a column of reference cells disposed in the row decoder. BLS/BLE control logic circuitry is operable to fine-tune the WL pulse width so as to minimize dead time and power consumption in access cycle operations.
In one aspect, the present invention is directed to a self-referenced timing system having a built-in shutdown apparatus for coordinating memory access operations. Wordline control circuitry is provided which includes an address decode block operable to generate a wordline start (WLS) signal, a reference cell portion for operating responsive to the WLS signal, a wordline generator block coupled to the reference cell portion for generating a wordline (WL) signal with respect to a memory access operation and a wordline shutdown feedback block operable to generate a wordline end (WLE) signal that feeds back to the reference cell portion. The reference cell portion, operating under a bitline start (BLS) control block and a bitline end (BLE) control, is used for controlling the timing loop of the memory access operation.
In another aspect, the present invention is directed to a self-referenced timing system for memory access operations, which includes circuitry for selecting a particular wordline in a memory circuit for an access operation, and circuitry for deselecting the particular wordline responsive to a shutdown feedback signal derived from the particular wordline.
In yet another aspect, the present invention is directed to a read access operation method in a memory circuit. Responsive to a clock signal provided to the memory circuit, a BLS control signal is generated. A selected WL in the memory circuit is activated based on a plurality of address signals. Thereafter, a self-referenced feedback control signal generated based on the WL signal is provided to a reference cell disposed in a row decoder of the memory circuit. Subsequently, a BLE control signal operable to drive the WL signal LOW is generated when a voltage level on the BLE control signal reaches a particular value.
In a still further aspect, the present invention is directed to a write access operation method in a memory circuit. As with the read access operations, responsive to a clock signal provided to the memory circuit, a BLS control signal associated with a reference cell disposed in a row decoder of the memory circuit is generated. Also, a bitline associated with a selected core cell is also driven LOW, but at a much faster rate than t
Pandey Rohit
Raszka Jaroslav
Danamraj & Youst P.C.
Tran Andrew Q.
Virage Locic Corp.
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