Burst EDO memory device with maximized write cycle timing

Details Burst EDO memory device with maximized write cycle timing Burst EDO memory device with maximized write cycle timing

1997-02-10

1998-02-10

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365233, 36518905, G11C 700

Patent

active

057176540

ABSTRACT:
An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access, reset the burst length counter and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies.

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