Burst EDO memory address counter

Details Burst EDO memory address counter Burst EDO memory address counter

1997-09-02

1998-12-15

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Byte or page addressing

365236, G11C 800

Patent

active

058503684

ABSTRACT:
A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combination with a sequence select signal are logically combined to produce a multiplexer select input which selects between true and compliment outputs of a first flip flop to couple to an input of a second flip flop to specify a toggle condition for the second flip flop. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access. A transition of the Read/Write control line during a burst access will terminate the burst access and initialize the device for another burst access.

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