Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-12-20
2001-03-20
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S230010, C365S230010
Reexamination Certificate
active
06205084
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor storage systems and methods, and more particularly, to methods and systems of performing memory operations for accessing data in a burst mode transfer data storage environment, especially non-volatile semiconductor memory devices such as flash memory devices.
Generally, a flash memory device comprises an address sequencer, row and column decoders, sense amplifiers, write amplifiers, and a memory cell array. An example of a flash memory device is described in U.S. Pat. No. 5,490,107, the disclosure of which is herein incorporated by reference. The memory cell array contains a plurality of memory cells arranged in rows and columns. Each memory cell is capable of holding a single bit of information.
The memory cells in the memory cell array of a flash memory device are generally grouped into sub-arrays called memory cell blocks. Each memory cell block is coupled to a sense amplifier and a write amplifier. The write amplifier (W/A) applies a set of predetermined voltages to store information in the selected memory cells. This action is referred to as a program or write operation. Similarly, a set of predetermined voltages applied to the selected memory cells allows information to be discriminated and retrieved by the sense amplifier (S/A). This action is referred to as a read operation.
Generally, a read operation or a write operation is initiated in response to external signals provided by a controller, such as a processor. Likewise, information read or written into the flash memory device is generally transferred to and from the processor. In most cases, the amount of information transferred is large. Also, the rate at which the information is propagated from a controller to the flash memory device and vice versa is ever increasing. Therefore, increasing performance demands are constantly being imposed on a processor, the flash memory device, and also the communication interface between the processor and the flash memory device.
For instance, the processor, flash memory and other peripheral devices must compete for the use of the communication interface, e.g., a bus. However, a bus has a limited bandwidth for transferring information to and from the peripherals. Therefore, efficient bus utilization is generally highly desirable. Burst mode technology is one way to efficiently utilize the bus and to increase bus bandwidth. Burst mode technology combines individual read requests and write requests to memory into aggregates, with each aggregate being formed of many individual read requests or write requests. Burst mode technology transfers these aggregates in bursts, such that an aggregate of individual read requests are transferred followed by an aggregate of individual write requests. Therefore, groups of read or write requests can be serviced at the same time instead of individually, and therefore decrease bus overload and effectively increase bus bandwidth.
Also, the speed of read and write operations is often increased in order to realize higher performance flash memory devices. One such method to increase the speed of read operations is synchronization. By synchronizing the read operations to an external clock, the speed of the read operations is improved.
However, often the processor selects or enables only one of the peripherals to utilize the bus at any given time. The selection of the peripherals is usually performed in a predetermined order or randomly. Under certain conditions, a read operation may take longer to stabilize when the flash memory is enabled. The delay is often greater than one clock period of an external clock and thus disrupts the synchronization of the read operation to the external clock. As a result, incorrect data can be read from the selected memory cell. Therefore, the use of both burst mode technology and flash memory operations is therefore problematical.
Furthermore, the use of burst mode technology, generally, require an initial latency time in performing a memory operation. In some cases, the initial latency is required to prevent any disruption in operation of a peripheral operating at a low clock frequency. However, in cases in which the peripheral, such as the flash memory device, that operates at a high clock frequency, the initial latency can be bypassed to improve the performance speed of the flash memory device. Accordingly, methods and systems which overcome the obstacles of using of both burst mode technology and flash memory operations are desirable. Furthermore, increasing performance speed of the flash memory device using burst mode technology is also desirable.
SUMMARY OF THE INVENTION
The present invention therefore provides a burst mode flash memory device. In one embodiment the burst mode flash memory device synchronously operates with an external clock and comprises a memory cell array having a plurality of memory cells, each memory cell storing data. The memory device additionally includes input circuits selecting a subset of memory cells and generating an internal clock synchronized to the external clock, with the generation of the internal clock delayed upon receipt of a predefined control signal. The memory device additionally includes reader circuits fetching data stored in the subset of memory cells selected, and output circuits outputting the data fetched in a predetermined grouping and synchronously with the internal clock. In a further embodiment the burst mode flash memory device comprises a delay circuit receiving a signal corresponding to the predefined control signal and generating an internal enable signal which is a delayed version of the predefined control signal. The input circuit additionally comprises an internal clock generator circuit generating internal clock signals using an external clock signal, with at least one of the internal clock signals being generated only when the internal enable signal is in a first state.
In an additional embodiment a flash memory device has a memory cell array, an address decoder for processing address information used in accessing the memory cell array, a method of increasing reliability of access of the memory cell array comprising receiving an output enable signal and forming a delayed enable signal. A method additionally comprises providing a delayed output enable signal to an internal clock generator, the delayed output enable signal being used to enable an internal clock signal, and generating the internal clock signal for use in accessing the memory cell array.
A further embodiment of the present invention comprises a flash memory device including a handshake circuit comprising a comparator which compares least significant address signals generated by the address signal generator and forms a control signal, a shift circuit for phase shifting the external clock signal, and a gate circuit for gating the shifted clock signal.
A further embodiment of the present invention comprises a flash memory device having an output buffer comprising a first data path and a second data path. The first data path receives an input signal and outputs an output signal and includes a plurality of latches. A second data path includes a portion of the first data path and a bypass portion by passing at least one latch in the first data path, with the second data path being controlled by a gate controlled by a signal indicative of a transition and an address signal. In a further embodiment the present invention comprises a decoder counter selector for a flash memory device. The decoder counter selector includes comparators for finding bit patterns of a plurality of address signals. The decoder counter selector further includes a plurality of shift register in a sequence, each shift register receiving two match signals additionally received by shift registers adjacent in the sequence and outputting an output signal for selecting a latch buffer for driving an output of the memory.
Many of the attendant features of this invention will be more readily appreciated as the same becomes better understood by reference to the fo
Christie Parker & Hale LLP
Fujitsu Limited
Nguyen Tan T.
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