Buffer memory for an input line of a digital interface

Details Buffer memory for an input line of a digital interface Buffer memory for an input line of a digital interface

1985-04-30

1988-07-05

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Sync/clocking

365230, 365189, 370102, G11C 800

Patent

active

047559713

ABSTRACT:
A buffer memory for an input line of a digital interface serves to adapt input data which exhibit large phase fluctuations with respect to the local clock of the interface to this local clock. To this end it is necessary to write the input data with the associated clock into the buffer, the data being read with the local clock. Depending on the phase shifts, write and read operation are then liable to occur simultaneously in border cases. In order to enable the use of conventional components in spite of the described phenomenon, the buffer memory is composed of a number of storage blocks which each comprise the same number of addresses, the storage blocks normally being cyclically addressed in succession. An address spacing monitoring device ensures that read and write operations are always performed only in different storage blocks, so that they can take place simultaneously. When the spacing between read and write operations becomes less than the number of address positions of a storage block due to prolonged, large phase fluctuations so that there is a risk of simultaneous read and write operations within the same block, a read address jump is made in order to address a next or a preceding storage block so that the address is increased again. This address jump takes place only at or directly after the changing over of notably the read address from one storage block to another.

REFERENCES:
patent: 4287577 (1981-09-01), Deal, Jr.
patent: 4397017 (1983-08-01), Rokugo
patent: 4423493 (1983-12-01), Annecke
patent: 4433394 (1984-02-01), Torii et al.
patent: 4525849 (1985-06-01), Wolf

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