Burst order control circuit and method thereof

Details Burst order control circuit and method thereof Burst order control circuit and method thereof

2011-08-09

2011-08-09

Dinh, Son T (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S230060

Reexamination Certificate

active

07995422

ABSTRACT:
A burst order control circuit includes a burst signal generating unit configured to receive a seed column address and to generate a first rising burst signal, a second rising burst signal, a first falling burst signal and a second falling burst signal in response to the seed column address, and a repeater unit configured to transfer the first rising burst signal, the second rising burst signal, the first falling burst signal and the second failing burst signal to a pipe latch.

REFERENCES:
patent: 2003/0086515 (2003-05-01), Trans et al.
patent: 2008/0165594 (2008-07-01), Kim
patent: 1019970060223 (1997-08-01), None
patent: 1019980066901 (1998-10-01), None
Notice of Allowance issued from Korean Intellectual Property Office on Nov. 30, 2010.

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