Static information storage and retrieval – Addressing – Counting
Reexamination Certificate
2002-10-10
2004-07-06
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Addressing
Counting
C365S230010, C365S230030, C365S238500, C365S239000
Reexamination Certificate
active
06760274
ABSTRACT:
BACKGROUND OF THE INVENTION
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCS have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU's bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAM's can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device that can operate in a manner similar to SDRAM operation.
SUMMARY OF THE INVENTION
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
A synchronous non-volatile memory, in one embodiment, comprises an array of non-volatile memory cells arranged in addressable rows and columns, and a plurality of column address signal inputs. A column address counter circuitry is coupled to access the array in response to the plurality of column address signal inputs. The column address counter circuitry identifies any 2
N
column addresses of the array by modifying only N least significant column address signal inputs of the plurality of column address signal inputs. In another embodiment, the synchronous non-volatile memory further comprises a programmable mode register to store a burst length code indicating a burst length of 2
N
. The programmable mode register can be non-volatile. In yet another embodiment, 2
N
is 2, 4 or 8 and the N least significant column address signal inputs are 1, 2 or 3 column address inputs, respectively.
A method of reading a non-volatile synchronous memory device is provided. The method comprises receiving an initial column address on column address inputs A
0
, A
1
, A
2
, A
3
, A
4
, A
5
, A
6
and A
7
, wherein A
0
is a least significant address input. A burst read operation is initiated and has specified a burst length. Using an internal counter circuit, additional column addresses are generated starting at the initial column address. The internal counter changes a signal only on column address input A
0
if the burst length is two. The internal counter changes signals only on column address inputs A
0
and A
1
if the burst length is four. The internal counter changes signals only on column address inputs A
0
, A
1
and A
2
if the burst length is eight.
In one embodiment, the additional column addresses are generated in accordance with an order of column address accesses provided as, where the column address access number indicates a binary state of the column address bits:
Burst
Initial Column Address
Order of column
Length
A2
A1
A0
address accesses
2
0
0-1
1
1-0
4
0
0
0-1-2-3
0
1
1-2-3-0
1
0
2-3-0-1
1
1
3-0-1-2
8
0
0
0
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
0
1
0
2-3-4-5-6-7-0-1
0
1
1
3-4-5-6-7-0-1-2
1
0
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
1
1
1
7-0-1-2-3-4-5-6
In another embodiment, the additional column addresses are generated in accordance with an order of column address accesses provided as:
Burst
Initial Column Address
Order of column
Length
A2
A1
A0
address accesses
2
0
0-1
1
1-0
4
0
0
0-1-2-3
0
1
1-0-3-2
1
0
2-3-0-1
1
1
3-2-1-0
8
0
0
0
0-1-2-3-4-5-6-7
0
0
1
1-0-3-2-5-4-7-6
0
1
0
2-3-0-1-6-7-4-5
0
1
1
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
1
0
1
5-4-7-6-1-0-3-2
1
1
0
6-7-4-5-2-3-0-1
1
1
1
7-6-5-4-3-2-1-0
Another method of reading a non-volatile synchronous memory device is provided. The method comprises initiating a burst read operation by providing control signals from an processor device coupled to the non-volatile synchronous memory device, coupling an initial column address from the processor to the non-volatile synchronous memory device, and generating a series of column addresses using an internal address counter of the non-volatile synchronous memory device. The series of column addresses starts at the externally provided initial column address. The series of column addresses comprise 2
N
column addresses and the series is generated by modifying only N least significant column address signal inputs.
Yet another method of reading data from a non-volatile memory device is provided. The method comprises selecting a read burst length of 2
N
, receiving an initial column address, and defining a plurality of column addresses having upper and lower column address boundaries based upon the initial column address and the read burst length. The plurality of column addresses comprises 2
N
column addresses of the non-volatile memory device, and are defined by modifying only N least significant column address bits of the initial column address.
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Leffert Jay & Polglaze P.A.
Nguyen Viet Q.
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