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Data input/output system for multiple data rate memory devices

Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate

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Data latch circuit of semiconductor device and method for...

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Data latch controller of synchronous memory device

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Data line potential setting circuit and MIS memory circuit using

Static information storage and retrieval – Addressing
Patent

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Data masking circuits and methods for integrated circuit memory

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Data masking systems and methods for integrated circuit memory d

Static information storage and retrieval – Addressing – Plural blocks or banks
Patent

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Data output buffer

Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Patent

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Data output buffer of a semiconducter memory device

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Data output buffer of a synchronous semiconductor memory device

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Data output circuit having shared data output control unit

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Data output circuits for semiconductor memory devices

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Data output control circuit

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Data output control circuit of a double data rate (DDR)...

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Data output controller in semiconductor memory device and...

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Data output device for synchronous memory device

Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate

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Data output equipment for a semiconductor memory device

Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Patent

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Data pass control device for masking write ringing in DDR...

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Data path reset circuit using clock enable signal, reset...

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Data processing apparatus having address decoder supporting wide

Static information storage and retrieval – Addressing – Multiplexing
Patent

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Data processing device

Static information storage and retrieval – Addressing – Multiple port access
Patent

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