Data processing apparatus having address decoder supporting wide

Details Data processing apparatus having address decoder supporting wide Data processing apparatus having address decoder supporting wide

1991-04-24

1994-04-19

Heyman, John S.

Static information storage and retrieval

Addressing

Multiplexing

36523006, 36523008, 307463, G11C 700

Patent

active

053052773

ABSTRACT:
An address decoder is connected to an address bus and comprises a plurality of latches for latching address signals from the address bus. Decode logic is connected to use unlatched addresses from the address bus or latched addresses from the latches. The decoder is selectively operable to decode addresses in two modes, an unlatched mode and a latched mode dependent upon system frequency. The decode logic produces a signal that is transmitted into a state machine for controlling operation thereof.

REFERENCES:
patent: 4750839 (1988-06-01), Wang et al.
patent: 4766572 (1988-08-01), Kobayashi
patent: 4897819 (1990-01-01), Takizawa
patent: 4970692 (1990-11-01), Ali et al.
patent: 5005157 (1991-04-01), Catlin
patent: 5148535 (1992-09-01), Ballard

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