Data output buffer of a synchronous semiconductor memory device

Details Data output buffer of a synchronous semiconductor memory device Data output buffer of a synchronous semiconductor memory device

1993-10-04

1995-01-24

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 365193, G11C 800

Patent

active

053847504

ABSTRACT:
A data output buffer is used for a synchronous semiconductor memory device carrying out a data read/write operation in synchronism with an externally supplied clock. The semiconductor memory device includes a first shift register having a plurality of clock stages for transmitting a RAS signal in response to the clock; a circuit for extracting a data output margin signal from a predetermined stage among the stages of the first shift circuit; first latch circuits each receiving the data output margin signal, for generating a plurality of first latency signals having information on the RAS signal by combining row address signals and the signals extracted from the respective clock stages of the first shift circuit; a second shift circuit having a plurality of clock stages for transmitting a CAS signal in response to the clock; second latch circuits each receiving the data output margin signal, for generating a plurality of second latency signals having information on the CAS signal by combining column address signals and the signals extracted from the respective clock stages of the second shift circuit; and a latency combination circuit receiving the first and second latency signals, for generating a data output control signal to the data output buffer, so that the data output buffer can generate data output even during a RAS precharge cycle.

REFERENCES:
patent: 4719601 (1988-01-01), Gray et al.
patent: 5287327 (1994-02-01), Takasugi

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