Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2006-06-29
2008-11-25
Nguyen, Dang T (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S193000, C365S194000
Reexamination Certificate
active
07457190
ABSTRACT:
Disclosed is a data input circuit of a synchronous memory device for detecting and amplifying data, and transferring the amplified data for storage, which including: a write strobe signal converter for receiving a write strobe signal, dividing the received write strobe signal, and outputting control signals of predetermined bits, the control signals being synchronized with rising and falling edges of the divided signal; and a latch unit for latching data corresponding to the bits by means of the control signals, and outputting the data for the detection and amplification of the data. The data input circuit may include a first delay unit for delaying the data in order to match setup-hold time, a second delay unit for performing delay for adjusting the data outputted from the latch unit, and a third delay unit for performing delay for adjusting the write strobe signal outputted from the latch unit.
REFERENCES:
patent: 7042799 (2006-05-01), Cho
patent: 2004/0218429 (2004-11-01), Shim
patent: 2006/0215467 (2006-09-01), Partsch
patent: 2007/0002644 (2007-01-01), Kang
patent: 2007/0282555 (2007-12-01), Chong et al.
patent: 2002-0086197 (2002-11-01), None
Hynix / Semiconductor Inc.
Ladas & Parry LLP
Nguyen Dang T
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