Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2003-07-22
2004-11-30
Phung, Anh (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230030
Reexamination Certificate
active
06826114
ABSTRACT:
BACKGROUND OF THE INVENTION
This application claims the priority of Korean Patent Application No. 2002-55008, filed 11, Sep. 2002, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to the resetting of a data path in a synchronous semiconductor memory device.
2. Description of the Related Art
A reset in a synchronous semiconductor memory device can be regarded as either a hard reset or a soft reset. In a case where a computer system including the synchronous semiconductor memory device is reset by turning the computer off and on, the hard reset is applied to the semiconductor memory device, and then a subsequent process is performed. However, in a case where the computer system is reset by using a reset key or a specific key of the computer system, the soft reset is applied to the synchronous computer system, and then a subsequent process is performed.
In the case where the soft reset is applied to the synchronous semiconductor memory device which operates synchronously with a clock signal, a level of an external voltage VCC may not be completely lowered to 0V. That is, rather than the level of the external voltage VCC being lowered to 0V and then raised to its initial level, the external voltage VCC may be barely lowered at all. In the case in which the hard reset is applied to. the synchronous semiconductor memory device, the level of the external voltage VCC is lowered to 0V and then raised to its initial level.
Most dynamic random access memory (DRAM) generates a control signal used for detecting the level of the external voltage VCC and resetting all internal nodes of the DRAM. However, when the soft reset is applied by lowering the external voltage VCC by a small amount, it is difficult to detect such a small change in the level of the external voltage VCC and reset all internal nodes of the DRAM.
Current double data rate (hereinafter, referred to as DDR) synchronous dynamic random access memory (SDRAM) devices prevent the execution of the soft reset, i.e., the application of a clock enable signal (CKE) having a low level, while a data path is operating. However, if a control signal related to the data path is not reset to a low level when a soft reset is desired during an operation of a read command or a write command, a problem such as data conflict can be caused when a read command or a write command is applied.
In the case of a hard reset, the level of the external voltage VCC is lowered to 0V and then returns to its initial level, and internal circuits are reset. However, in some cases, a desired internal circuit is not reset in a soft reset where the level of the external voltage changes only slightly. Thus, an abnormal function occurs in which data are continuously output even though the soft reset is applied.
In current DDR SDRAM devices, the low level clock enable signal CKE is always applied during the soft/hard resets. Therefore, if the control signal related to an output driver and the data path are reset when the clock enable signal CKE is at the low level, data conflicts do not occur in executing operations according to next commands.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a circuit and a method which make it possible to reset blocks and control signals related to a data path in a soft reset, thereby performing an operation according to a next command without any errors, and a semiconductor memory device including the circuit and adopting the method.
According to an aspect of the present invention, there is provided a reset signal generating circuit in a semiconductor memory device. The circuit comprises an external voltage detector which detects a level of an external voltage and generates a first reset signal, and a second reset signal generator which performs a logical sum of an external signal and the first reset signal, and outputs the result of the logical sum as a second reset signal. The second reset signal is used to reset a block related to a data path of the semiconductor memory device.
Preferably, the first reset signal is used to reset blocks other than the block related to the data path.
The external signal can be a clock enable signal. The second reset generator can include an automatic pulse generator which generates a pulse signal which maintains a first logic level during a predetermined period in response to the clock enable signal, and a logical sum gate which logically sums the pulse signal and the first reset signal, and outputs the result as the second reset signal.
The block related to the data path can further include a data output driver for performing a driving operation for outputting the data, which is output via a pad from the memory cell and then detected. The block related to the data path can further include a data input driver which performs a driving operation on the data which is externally input through the pad. The block related to the data path can include at least a part of a data output circuit in a path from an output node of an input/output sense amplifier which senses and amplifies the data output from a memory cell to an input/output pad.
According to another aspect of the present invention, there is provided a semiconductor memory device comprising a memory cell array, a row decoder which selects and activates a word line of the memory cell array in response to a row address signal, a column decoder which selects a column line of the memory cell array in response to a column address signal, an input/output sense amplifier which senses and amplifies the data output from the memory cell array, a data line driver for inputting the data in the memory cell array, a data output unit which outputs through an input/output port the data output from the input/output sense amplifier, a data input unit which transmits the data input from input/output pad to the data line driver, a control logic unit which generates a plurality of control signals in response to an address signal and a command signal, and a reset signal generating circuit which generates a first reset signal and a second reset signal in response to an external voltage and an external signal, wherein the data output unit is at least partially reset in response to the second reset signal.
Preferably, the reset signal generating circuit comprises an external voltage detector which detects the level of the external voltage and generates the first reset signal, and a second reset signal generator which performs a logical sum of a clock enable signal, which is externally input, and the first reset signal, and outputs the result of the logical sum as the second reset signal.
In one embodiment, the second reset signal generator comprises an automatic pulse generator which generates a pulse signal which maintains a first logic level for a predetermined period in response to the clock enable signal, and a logical sum gate which performs a logical sum of the pulse signal and the first reset signal, and outputs the second reset signal.
In one embodiment, the second reset signal is also used to reset at least a part of the data input unit.
According to another aspect of the present invention, there is provided a method for resetting an internal circuit of a semiconductor memory device, the method comprising detecting the level of an external voltage and generating a first reset signal, logically summing an external signal and the first reset signal and generating a second reset signal, resetting a block related to a data path in response to the second reset signal, and resetting blocks other than the block related to the data path in response to the first reset signal.
In one embodiment, the external signal is a clock enable signal.
In one embodiment, step (b) further comprises generating a pulse signal which maintains a first logic level for a period of time in response to the clock enable signal and performing a logical sum of the pulse signal and the
Jung Won-chang
Lee Jung-bae
Mills & Onello LLP
Phung Anh
LandOfFree
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