Data output controller in semiconductor memory device and...

Details Data output controller in semiconductor memory device and... Data output controller in semiconductor memory device and...

2006-06-27

2006-06-27

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189020, C365S189050, C365S189120, C365S194000

Reexamination Certificate

active

07068567

ABSTRACT:
A data output controller of a high-speed memory device and a method therefor. The data output controller includes a first section for detecting a unit delay multiple of an external clock signal based on the external clock signal and a delay circuit of the external clock signal, a second section for analyzing data in an information storage unit, in which an internal timing is defined, by using values detected by the first section, and a third section for adjusting a data output timing in accordance with predetermined CAS latency based on analyzed values obtained through the second section. The data output controller to indicate an optimal point of a data output indicated by CAS latency information.

REFERENCES:
patent: 6985401 (2006-01-01), Jang et al.

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