Data output control circuit

Details Data output control circuit Data output control circuit

2006-01-03

2006-01-03

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06982924

ABSTRACT:
A data output control circuit for use in a synchronous semiconductor memory device including: a first data output enable signal generation unit for receiving an internal signal and generating a rising data output enable signal synchronizing with a rising edge of a DLL clock signal according to a CAS latency; and a second data output enable signal generation unit for receiving the rising data output enable signal and generating a falling data output enable signal synchronizing with a falling edge of the DLL clock signal.

REFERENCES:
patent: 6266294 (2001-07-01), Yada et al.
patent: 6512719 (2003-01-01), Fujisawa et al.
patent: 6707758 (2004-03-01), Kono
patent: 6850458 (2005-02-01), Li

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