Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Patent
1994-04-06
1995-04-11
Fears, Terrell W.
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
365206, 36518905, G11C 1300
Patent
active
054065283
ABSTRACT:
A data output buffer in a semiconductor memory device capable of minimizing generation of ground noise in data being transmitted to an external circuit device via an output line. The data output buffer includes a first input line for inputting true data, a second input line fox inputting complement data, a pull-up transistor connected among a first power supply source, an output line and the first input line, a pull-down transistor connected among a second power supply source, the output line and the second input line, and a resistance-varying transistor for controlling an amount of current being supplied from the second input line to the pull-down transistor, and thereby removing a noise signal to be included in output data of low logic on the output line.
REFERENCES:
patent: 5088062 (1992-02-01), Shikata
Fears Terrell W.
Hyundai Electronics Industries Co,. Ltd.
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