Data latch circuit of semiconductor device and method for...

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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C365S189050, C365S205000

Reexamination Certificate

active

11319614

ABSTRACT:
A data latch circuit for latching a data and a method for latching a data signal in synchronization with a clock signal are provided. The data latch circuit includes: a data input controller for outputting a first data transition detection signal in response to a first transition point of the data signal, and outputting a second data transition detection signal in response to a second transition point of the data signal; and a data latch unit for starting latching the data signal in response to the first data transition detection signal and finishing latching the data signal in response to the second data transition detection signal, wherein the data latch unit deactivates the first data transition detection signal corresponding to the start of latching the data signal, and outputs a feedback signal for deactivating the second data transition detection signal corresponding to the finish of latching the data signal.

REFERENCES:
patent: 5015891 (1991-05-01), Choi
patent: 5757718 (1998-05-01), Suzuki
patent: RE35847 (1998-07-01), Lee
patent: 6154417 (2000-11-01), Kim
patent: 6498766 (2002-12-01), Lee et al.
patent: 3-130991 (1991-06-01), None
patent: 10-208483 (1998-08-01), None

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