Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2008-05-28
2010-12-14
Tran, Andrew Q (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S233110, C365S233120, C365S233130, C365S189050, C365S193000, C365S194000, C326S028000, C326S096000, C326S095000
Reexamination Certificate
active
07852707
ABSTRACT:
A semiconductor memory device using system clock with a high frequency can maintain a constant margin of operation even with a changed operating environment including voltage level, temperature, and process. The semiconductor memory device includes a data output control circuit configured to control data outputted in synchronization with a falling edge of a system clock using a first output source signal corresponding to a rising edge of the system clock, and to control data outputted in synchronization with the rising edge of the system clock using a second output source signal corresponding to a falling edge of the system clock, and a data output circuit configured to output data, the data output circuit being controlled by the data output control circuit.
REFERENCES:
patent: 7715253 (2010-05-01), Kim et al.
patent: 2003/0223279 (2003-12-01), Lee
patent: 2005/0174860 (2005-08-01), Kim et al.
patent: 1020050041613 (2005-05-01), None
patent: 1020060032428 (2006-04-01), None
patent: 1020060053431 (2006-05-01), None
patent: 1020060054610 (2006-05-01), None
Hynix / Semiconductor Inc.
IP & T Group LLP
Tran Andrew Q
LandOfFree
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