Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-06-06
2001-08-14
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230030, C365S203000, C365S230080, C365S233100
Reexamination Certificate
active
06275441
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to integrated circuits and in particular to input/output (I/O) architecture and read/write system for high bandwidth semiconductor memories.
Increasing speed of operation and bandwidth have been major driving forces behind evolutionary changes in the design and development of memory circuits. In the case of dynamic random access memories (DRAMs), for example, the extended data output (EDO) architecture was developed to enhance memory bandwidth. With the introduction of the synchronous DRAM (SDRAM), the ability to pipeline the data as well as data pre-fetch schemes have helped increase the speed, throughput and bandwidth of the memory. This increase in bandwidth has not in all cases been without a tradeoff. The double data rate, or DDR SDRAM, for example, takes advantage of a two-bit pre-fetch technique to double the bandwidth of the memory circuit. This has been extended to quad data rate and above.
One drawback of these types of multiple data rate SDRAMs has been the corresponding increase in the number of I/O interconnect lines required to process the multiple bits during read and write operations. For example, in a DDR SDRAM having a by N (or xN, e.g., x16 or x32) organization, a 2-bit pre-fetch results in 2N bits of data being output from the memory array in read mode. Typically the total columns in an array are divided into two sets of even and odd columns, each delivering N bits of data. The 2N columns connect to a corresponding 2N sense amplifiers, with the 2N sense amplifiers driving 2N global I/O lines. A 2:1 parallel to serial conversion at the output takes place before the data is applied to the N data output (DQ) registers. The process is reversed for the write mode of operation wherein a serial-to-parallel conversion turns a serial bit stream into pairs of bits for DDR (quad bits for QDR, etc.).
Accordingly, a DDR SDRAM that has, for example, a x32organization and uses a complementary global I/O bus architecture (i.e., pair of lines per bit), requires 128 global I/O interconnect lines. Given an exemplary 2 micron pitch for each interconnect line, the 128 lines take up about 256 &mgr;m which may be as much as 5% of the die size. This large number of global I/O lines therefore appreciably increases the overall size and cost of the memory device.
SUMMARY OF THE INVENTION
The present invention provides methods and circuitry for implementing memory devices with I/O architectures that transmit multiple data bits on a data I/O interconnect line during a single clock cycle. Instead of increasing the physical number of I/O interconnect lines to match the increased number of data bits being processed by the multiple data rate memory circuit, the present invention provides a time sharing scheme that processes the multiple bits of data with a minimum number of I/O lines. In specific embodiments, the time sharing is accomplished in a self-timed manner to ensure accurate operation. In other embodiments, the present invention provides for further improvements by eliminating precharging when not necessary, and by using N double-ended data buses to transmit 2N single-ended data bits during the write mode of operation.
Accordingly, in one embodiment, the present invention provides a memory circuit that operates according to a periodic clock signal, the memory circuit including a plurality of data registers respectively coupled to a corresponding plurality of data buses, wherein the circuit is configured such that each data bus is capable of carrying more than one bit of data during a single period of the periodic clock signal. Further, the circuit is configured such that the more than one bit of data are transmitted in a self-timed manner wherein one edge of a first bit of data triggers an edge of a succeeding bit of data. In a specific embodiment, the circuit of the present invention further includes precharge control circuitry that is coupled to the plurality of data buses and is configured to precharge a data bus during the single period of the periodic clock only if the more than one data bits are different in binary value. In yet another specific embodiment, each of the plurality of data buses comprises a pair of interconnect lines to process double-ended read data bits, and the circuit is further configured to process single-ended data bits in write mode, wherein each interconnect line in the plurality of data buses carries one single-ended bit of write data during write mode.
In another embodiment the present invention provides in a synchronous memory circuit that has N data registers coupled to N data buses and operates according to a periodic clock signal, a method of transmitting data that includes transmitting a first bit of data during a first portion of a single period of the clock signal, and transmitting a second bit of data during a second portion of the single period of the clock signal. The method further including triggering an edge of the second bit of data in response to an edge of the first bit of data.
In yet another embodiment, the present invention provides a method of operating a semiconductor memory device, including: selecting a plurality of data in one clock cycle from an array of memory cells in read mode; determining a sequence of the plurality of data; time shifting each of the plurality of data according to the sequence; and driving the plurality of data onto a single data bus in the sequence within one clock cycle.
A better understanding of the nature and advantages of the data I/O technique of the present invention may be gained with reference to the following detailed description and the accompanying drawings.
REFERENCES:
patent: 5748917 (1998-05-01), Krein et al.
patent: 5802387 (1998-09-01), Boddie et al.
patent: 5978884 (1999-11-01), Yamaguchi et al.
patent: 6061779 (2000-05-01), Garde
patent: 6130558 (2000-10-01), Lee
G-Link Technology
Nelms David
Townsend & Townsend & Crew LLP
Yoha Connie C.
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