Selectable clock input

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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Details

C365S230010

Reexamination Certificate

active

11270578

ABSTRACT:
The present invention provides a memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a plurality of possible clock input signals, for example, a single clock input or differential clock input.

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patent: 6472904 (2002-10-01), Andrews et al.
patent: 6522599 (2003-02-01), Ooishi et al.
patent: 6687184 (2004-02-01), Johnson et al.
patent: 6757212 (2004-06-01), Hamamoto et al.

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