Self-enabling pulse-trapping circuit

Details Self-enabling pulse-trapping circuit Self-enabling pulse-trapping circuit

1997-08-19

1998-11-03

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Sync/clocking

365233, 36523008, G11C 800

Patent

active

058319328

ABSTRACT:
An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additional memory addresses. An external input is used to terminate and change a burst operation. Circuitry is provided to monitor the external input during burst operations and provide an appropriate control signal.

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