Scheme for increasing enable access speed in a memory device

Details Scheme for increasing enable access speed in a memory device Scheme for increasing enable access speed in a memory device

1999-02-18

2000-09-19

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Sync/clocking

365195, 36523005, G11C 800

Patent

active

061222216

ABSTRACT:
In a memory device having a power-down mode, an address transition detection (ATD) signal within the memory device is inhibited at a power-up transition, provided that a power-down transition which proceeded the power-up transition ensured bit line equalization. The wordlines of the memory device may be disabled during the power-down mode and subsequently enabled (e.g., after an address-matched delay, to ensure a valid address is available for the first access following power-down) in response to the power-up transition. The ATD signal may be inhibited by generating a pulse having an appropriate starting time, and of sufficient duration to decouple an ATD pulse generator from dynamic bit line equalization control circuitry within the memory device. Such a pulse may be generated by combining a pair of signals produced in response to the power-up transition, at least one of the signals being delayed in time with respect to the other. In some cases, the ATD signal may be prevented by latching an address at the memory device, following an indication that the memory device is about to enter the power-down mode.

REFERENCES:
patent: 5471432 (1995-11-01), Makihara
patent: 5493537 (1996-02-01), McClure
patent: 5825715 (1998-10-01), Rezeanu
Hirofumi Shinohare et al., "A 45-ns 256K CMOS Static RAM with a Tri-Level Word Line", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, pp. 929-934 (Oct. 1985).
Stephan T. Flannagan, et al., "Two 13-ns 64K CMOS SRAM's with Very Low Active Power and Improved Asynchronous Circuit Techniques", IEEE Journal of Solid-State Circuits, vol. SC-21, No.: 5, pp. 692-703 (Oct. 1985).

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