Selective edge phase mixing

Details Selective edge phase mixing Selective edge phase mixing

2007-11-12

2009-10-27

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233100, C365S120000, C327S175000

Reexamination Certificate

active

07609583

ABSTRACT:
Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and memory device configured to perform operations in synchronization with transitions of an externally provided clock signal. A selective edge phase mixing unit for the memory device may include a first logic gate that receives the clock signal at an input port and receives first control signals, and pull-up circuits in communication with an output of the first logic gate and first control signals. A second logic gate receives the clock signal at the input port and receives second control signals. Pull-down circuits are coupled to the second logic gate and the second control signals, wherein the pull-up circuits and the pull-down circuits are coupled to the output port to provide a duty cycle corrected clock signal to the memory device. Additional apparatus, systems, and methods are disclosed.

REFERENCES:
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patent: 5777500 (1998-07-01), Eitrheim
patent: 5930689 (1999-07-01), Wilhite et al.
patent: 7202722 (2007-04-01), Mahadevan et al.
patent: 7239560 (2007-07-01), Lee et al.
patent: 7307461 (2007-12-01), Nguyen et al.
patent: 2008/0056030 (2008-03-01), Cho

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