SDRAM with a maskable input

Details SDRAM with a maskable input SDRAM with a maskable input

1999-12-08

2001-05-29

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230080

Reexamination Certificate

active

06240043

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memories and, more particularly, to synchronous dynamic random access memory with data prefetch.
2. Background Description
Synchronous Dynamic Random Access Memory (SDRAM) chips are well known. Essentially, a state of the art SDRAM, is accessed by providing an initial memory location or address that identifies a first data access location in a string of serially accessed contiguous locations. The first address is known as the burst starting address and the data string is known as the burst or data burst. The burst may have a width, which may be 1 bit, 4 bits or 8 or more bits, and a length that may be 2, 4, 8 or more locations. Burst width and length are set at the SDRAM architecture designer's discretion and the result of numerous design trade offs. Internally to the SDRAM, during any particular access, all of the cells in the burst are accessed simultaneously in parallel and serialized for external burst transfers.
This serial external data transfer and parallel internal data transfer is also typically referred to as “data prefetch.” Thus, data is passed to or retrieved from the chip serially, i.e., externally, and data passed to the chip may then be written to the array in parallel or read from the array in parallel to be passed off chip serially. Using data prefetch reduces the number of external data lines, which decreases chip area. Also, prefetch allows accessing the array at a significantly lower frequency than the external data rate, providing higher frequency operation.
In what are known as double data rate (DDR) SDRAMs input data is provided at both the rising and falling clock edge. So, for a two bit prefetch, one input (DQ) is provided to two internal data lines each operating at half of the input frequency. One of the two internal data lines receives data on the rising clock edge, the other receives data on the falling clock edge. For example an 8 bit prefetch, one input signal is provided to 8 receivers, allowing the receiver outputs signals to run with a frequency, which is 8 times smaller. Thus, DDR SDRAM prefetch allows the core memory circuits to operate at a significantly relaxed pace even though the data is supplied to the memory at much higher data bandwidth.
FIG. 1
shows a write driver circuit
100
for a prior art SDRAM. The write driver
100
is typically included in a sense amplifier for writing input data
102
to a memory array
103
. A receiver
104
passes the input data when the receiver enable
106
is asserted. A latch
108
temporarily stores the data from the receiver
104
. The latched data is passed to the input of write driver
110
. When write enable
112
is asserted, write driver
110
passes the latched data to the memory array
103
for storage at a selected memory location. This approach is adequate when every data bit presented to the input is to be stored in the memory array
103
.
As SDRAM performance objectives and operating frequency are pushed, increasingly, there is a need to prefetch 2 or more data bits. Increasing the number of prefetch bits produces an effective external operating frequency that is independent of the array operating frequency. Existing prefetch architectures merely replicate both the inputs and the write drivers for the number of pre-fetched bits. This approach increases the number of data busses and its associated bus area, which in turn results in a larger SDRAM chip.
Data masking is also difficult to implement in prefetch architecture SDRAMs. The individual prefetch bits must carry their mask information. It is impractical to provide the same mask for the whole prefetch package, since some of the bits may be masked whereas others are not.
Further the existing Joint Electron Device Engineering Council (JEDEC) SDRAM standard provides for a burst interrupt. For example, a four bit write operation can be interrupted after the first 2 bits have been written to initiate another four bit write operation. However, as yet, interrupt handling has not been done in a prefetch architecture with more than two bits. So, for an 8 bit prefetch architecture when an 8 bit burst is interrupted after 4 bits, the four bits must be stored in the array while information in cells corresponding to the data bits after the interrupt should not be disturbed. State of the art prefetch architectures do not provide for this.
Thus, there is a need for a Dynamic Random Access Memory (DRAM) and in particular for synchronous DRAMs that allow externally selecting which input bits of a bit string are stored in the array.
SUMMARY OF THE INVENTION
It is therefore a purpose of the present invention to enable burst interrupt during write operations in a pre-fetch architecture the Dynamic Random Access Memory (DRAM);
It is another purpose of the present invention to decrease DRAM chip area.
The present invention is an integrated circuit including a random access memory (RAM), especially, a synchronous dynamic RAM (SDRAM) having a maskable data input. The SDRAM includes an xy data input register receiving a burst x bits long and, y bits wide corresponding to the number of data lines (DQs). The xy mask register is set, initially, such that all bits will be in a masked state. An xy mask register receives a corresponding unmask bit for each received data bit, each unmask bit indicating whether the corresponding data bit is stored in the SDRAM array. An enable buffer receives data outputs from the xy data input register and passes the individual data outputs to the array depending on corresponding mask states stored in the xy mask register. During an input prefetch, an interrupt may occur causing any received portion of the burst or prefetch to be stored in the array without disturbing memory locations corresponding to the balance or remaining bits of the prefetch.


REFERENCES:
patent: 5813023 (1998-09-01), Mclaury

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